`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:19:31 02/23/2014 
// Design Name: 
// Module Name:    slowclk 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module slowclk1( clk_old, clk_new);

input clk_old;
output reg clk_new = 1'b0;
reg [1:0] counter = 2'b0;

always@ (posedge clk_old) 
	counter <= counter + 2'b1;

always@ (posedge clk_old) begin
	if ( counter[1] == 1'b1 ) begin
	clk_new <= 1'b1;
	end
	
else begin
	clk_new <= 1'b0;
	end
	
end

endmodule
